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RT8287 ? ds8287-03 june 2012 www.richtek.com 1 ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. pin configurations (top view) 3a, 21v 500khz synchronous step-down converter general description the RT8287 is a synchronous step-down regulator with an internal power mosfet. it achieves 3a of continuous output current over a wide input supply range with excellent load and line regulation. current mode operation provides fast transient response and eases loop stabilization. fault condition protection includes cycle-by-cycle current limiting and thermal shutdown. an adjustable soft-start reduces the stress on the input source at startup. the RT8287 requires a minimal number of readily available external components, providing a compact solution. features z z z z z 3a output current z z z z z adjustable soft-start z z z z z 120m /40m internal power mosfet switch z z z z z internal compensation minimizes external parts count z z z z z fixed 500khz frequency z z z z z thermal shutdown protection z z z z z cycle-by-cycle over current protection z z z z z wide 4.5v to 21v operating input range z z z z z adjustable output from 0.808v to 15v z z z z z small 14-lead wdfn package z z z z z rohs compliant and halogen free ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. wdfn-14l 4x3 applications z distributive power systems z battery charger z dsl modems z pre-regulator for linear regulators vin sw sw sw agnd gnd gnd ss vcc sw boot pgood en fb 13 12 11 1 2 3 4 5 14 69 10 gnd 15 78 package type qw : wdfn-14l 4x3 (w-type) RT8287 lead plating system z : eco (ecological element with halogen free and pb free) marking information a8 ym dnn a8 : product code ymdnn : date code
RT8287 2 ds8287-03 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function pin description pin no. pin name pin function 1 vin supply input. vin supplies the power to the ic, as well as the step-down converter switches. drive vin with a 4.5v to 21v power source. bypass vin to gnd with a suitably large capacitor to eliminate noise on the input to the ic. 2, 3, 4, 5 sw switch node. sw is the switching node that supplies power to the output. connect the output lc filter from sw to the output load. note that a capacitor is required from sw to boot to power the high side switch. 6 boot high side gate drive boost input. boot supplies the drive for the high side n-mosfet switch. connect a 100nf or greater capacitor from sw to boot to power the high side switch. 7 en chip enable (active high). for automatic start-up, connect the en pin to vin with a 100k resistor. 8 fb feedback input. fb senses the output voltage to regulate said voltage. drive fb with a resistive voltage divider from the output voltage. the feedback threshold is 0.808v. 9 pgood power good output. the output of this pin is open-drain. power good threshold is 90% low to high and 70% high to low of regulation value. 10 ss soft-start control input. ss controls the soft-start period. connect a capacitor from ss to gnd to set the soft-start period. 11 vcc bias supply. decouple with 0.1 f to 0.22 f capacitor. the capacitance should be no more than 0.22 f. 12, 13 15 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 14 agnd analog ground. connect this pin to the system ground in pcb layout. typical application circuit table 1. recommended components selection v out (v) r1 (k ) r2 (k ) r t (k ) l ( h) c ou t ( f) 5 75 14.46 0 4.7 22 x 2 3.3 75 24.32 0 3.6 22 x 2 2.5 75 35.82 0 3.6 22 x 2 1.8 5 4.07 30 2 22 x 2 1.5 5 5.84 39 2 22 x 2 1.2 5 10.31 47 2 22 x 2 1.05 5 16.69 47 1.5 22 x 2 1.2v/3a vin pgood vcc boot fb sw 9 8 1 2, 3, 4, 5 6 l 0.1f r1 r2 v out 22f v in RT8287 11 c boot c out c in ss 10 r t c ss 47nf gnd 12, 13, 15 (exposed pad) en agnd pgood r3 100k 0.1f c c 7 on/off 14
RT8287 3 ds8287-03 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram s q r driver - + current sense amplifier pwm comparator oscillator 500khz ramp generator regulator reference + - v c error amplifier sw boot fb en vin gnd + - + 10a ss + - pgood vcc v a v a v c 400k 30pf 1pf + - 1.2v + - 1.7v 1a 3v 5k lockout comparator shutdown comparator
RT8287 4 ds8287-03 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. absolute maximum ratings (note 1) z supply input v oltage, vin ---------------------------------------------------------------------------------- ? 0.3v to 26v z switch voltage, sw ----------------------------------------------------------------------------------------- ? 0.3v to (v in + 0.3v) z boot voltage, boot ----------------------------------------------------------------------------------------- (sw ? 0.3v) to (sw + 6v) z other pins ------------------------------------------------------------------------------------------------------ ? 0.3v to 6v z power dissipation, p d @ t a = 25 c wdfn-14l 4x3 ------------------------------------------------------------------------------------------------ 1.667w z package thermal resistance (note 2) wdfn-14l 4x3, ja ------------------------------------------------------------------------------------------ 60 c/w wdfn-14l 4x3, jc ------------------------------------------------------------------------------------------ 7 c/w z junction temperature ---------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ------------------------------------------------------------------ 260 c z storage temperature range ------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body model) --------------------------------------------------------------------------------- 2kv recommended operating conditions (note 4) z supply input voltage, vin ---------------------------------------------------------------------------------- 4.5v to 21v z junction temperature range ------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ------------------------------------------------------------------------------- ? 40 c to 85 c electrical characteristics parameter symbol test conditions min typ max unit shutdown current i shdn v en = 0 -- 0 1 a quiescent current i q v en = 2v, v fb = 1v -- 0.7 -- ma upper switch on resistance r ds(on)1 -- 120 -- m lower switch on resistance r ds(on)2 -- 40 -- m switch leakage i leak v en = 0v, v sw = 0v or 12v -- 0 10 a current limit i limit v boot ? v sw = 4.8v 5.4 6.5 -- a oscillator frequency f sw v fb = 0.75v 425 500 575 khz short circuit frequency v fb = 0v -- 150 -- khz maximum duty cycle d max v fb = 0.8v -- 90 -- % minimum on time t on -- 100 -- ns feedback voltage v fb 4.5v v in 21v 0.796 0.808 0.82 v feedback current i fb -- 10 50 na logic-high v ih 2 -- 5.5 en threshold voltage logic-low v il -- -- 0.4 v v en = 2v -- 1 -- enable current v en = 0v -- 0 -- a (v in = 12v, t a = 25 c unless otherwise specified)
RT8287 5 ds8287-03 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. parameter symbol test conditions min typ max unit power good rising threshold -- 90 -- % power good falling threshold -- 70 -- % power good delay -- 20 -- s power good sink current capability sink 4ma -- -- 0.4 v power good leakage current -- 10 -- na under voltage lockout threshold v uvlo v in rising 3.8 4 4.2 v under voltage lockout threshold hysteresis v uvlo -- 400 -- mv vcc regulator -- 5 -- v vcc load regulation i cc = 5ma -- 5 -- % soft-start period t ss c ss = 47nf -- 4.7 -- ms thermal shutdown t sd -- 150 -- c thermal shutdown hysteresis t sd -- 30 -- c note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability.bsolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions.
RT8287 6 ds8287-03 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. output voltage vs. output current 1.210 1.212 1.214 1.216 1.218 1.220 1.222 1.224 1.226 0 0.5 1 1.5 2 2.5 3 output current (a) output voltage (v) v in = 12v, v out = 1.22v, i out = 0a to 3a reference voltage vs. temperature 0.76 0.77 0.78 0.79 0.80 0.81 0.82 0.83 0.84 -50 -25 0 25 50 75 100 125 temperature (c) reference voltage (v) typical operating characteristics switching frequency vs. input voltage 350 375 400 425 450 475 500 525 550 4 6 8 10 12 14 16 18 20 22 input voltage (v) switching frequency (khz) 1 v out = 1.22v, i out = 0.8a switching frequency vs. temperature 350 375 400 425 450 475 500 525 550 -50-25 0 25 50 75100125 temperature (c) switching frequency (khz) 1 v in = 12v, v out = 1.22v, i out = 1a efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1 1.5 2 2.5 3 output current (a) efficiency (%) v out = 1.22v, i out = 0a to 3a v in = 12v v in = 21v reference voltage vs. input voltage 0.790 0.795 0.800 0.805 0.810 0.815 0.820 0.825 0.830 4 6 8 10 12 14 16 18 20 22 input voltage (v) reference voltage(v)
RT8287 7 ds8287-03 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. current limit vs. input voltage 0 2 4 6 8 10 12 4 6 8 10 12 14 16 18 20 22 input voltage (v) current limit (a) current limit vs. temperature 3 4 5 6 7 8 9 10 11 -50-25 0 25 50 75100125 temperature (c) current limit (a) v in = 12v, v out = 1.22v v in = 12v, v out = 1.22v, i out = 0a to 3a load transient response time (100 s/div) i out (2a/div) v out (200mv/div) output voltage ripple time (1 s/div) i l (2a/div) v sw (10v/div) v in = 12v, i out = 1a v out (50mv/div) v out (50mv/div) output voltage ripple time (1 s/div) i l (2a/div) v sw (10v/div) v in = 12v, i out = 3a v in = 12v, v out = 1.22v, i out = 1a to 3a load transient response time (100 s/div) i out (2a/div) v out (200mv/div)
RT8287 8 ds8287-03 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. power on from v in time (5ms/div) i l (5a/div) v out (1v/div) v in (10v/div) v in = 12v, v out = 1.22v, i out = 3a v pgood (5v/div) power on from en time (2.5ms/div) i l (5a/div) v out (1v/div) v en (5v/div) v in = 12v, v out = 1.22v, i out = 3a v pgood (5v/div) power off from en time (50 s/div) i l (5a/div) v out (1v/div) v en (5v/div) v in = 12v, v out = 1.22v, i out = 3a v pgood (5v/div) power off from v in time (50ms/div) i l (5a/div) v out (1v/div) v in (10v/div) v in = 12v, v out = 1.22v, i out = 3a v pgood (5v/div)
RT8287 9 ds8287-03 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. application information the ic is a synchronous high voltage buck converter that can support the input voltage range from 4.5v to 21v and the output current can be up to 3a. output voltage setting the output voltage is set by an external resistive divider according to the following equation : ?? + ?? ?? out fb r1 v = v1 r2 RT8287 gnd fb r1 r2 v out figure 1. output voltage setting figure 2. external bootstrap diode where v fb is the feedback reference voltage 0.808v (typ.). the resistive divider allows the fb pin to sense a fraction of the output voltage as shown in figure 1. external bootstrap diode connect a 100nf low esr ceramic capacitor between the boot pin and sw p in as shown in figure 2. this capacitor provides the gate driver voltage for the high s ide mosfet. it is recommended to add an external bootstrap diode between an external 5v and boot pin for efficiency improvement when input voltage is lower than 5.5v or duty ratio is higher than 65% .the bootstrap diode can be a low cost one such as in4148 or bat54. the external 5v can be a 5v fixed input from system or a 5v output of the ic. note that the external boot voltage must be lower than 5.5v. soft-start the ic contains an external soft-start clamp that gradually raises the output voltage. the soft-start timing is programmed by the external capacitor between ss pin and gnd. the chip provides an internal 10 a charge current for the external capacitor. if 47nf capacitor is used to set the soft-start, the period will be 4.7ms (typ.). under voltage lockout threshold the ic includes an input under voltage lockout protection (uvlo). if the input voltage exceeds the uvlo rising threshold voltage (4.2v), the converter resets and prepares the pwm for operation. if the input voltage falls below the uvlo falling threshold voltage (3.8v) during normal operation, the device stops switching. the uvlo rising and falling threshold voltage includes a hysteresis to prevent noise caused reset. chip enable operation the en pin is the chip enable input. pulling the en pin low (<0.4v) will shut down the device. during shutdown mode, the ic quiescent current drops to lower than 1 a. driving the en pin high (>2v, < 5.5v) will turn on the device again. for external timing control (e.g.rc), the en pin can also be externally pulled high by adding a r en * resistor and c en * capacitor from the vin pin, as can be seen from the figure 5. an external mosfet can be added to implement digital control on the en pin when front age system voltage below 2.5v is available, as shown in figure 3. in this case, a 100k pull-up resistor, r en , is connected between v in and the en pin. mosfet q1 will be under logic control to pull down the en pin. to prevent enabling circuit when v in is smaller than the v out target value, a resistive voltage divider can be placed between the input voltage and ground and connected to the en pin to adjust ic lockout threshold, as shown in figure 4. for example, if an 8v output voltage is regulated from a 12v input voltage, the resistor r en2 can be selected to set input lockout threshold larger than 8v. sw boot 5v 100nf RT8287
RT8287 10 ds8287-03 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 3. enable control circuit for logic control with low voltage figure 4. the resistors can be selected to set ic lockout threshold out out l in vv i = 1 fl v ??? ? ?? ??? ? ??? ? out out l(max) in(max) vv l = 1 fi v ??? ? ? ??? ? ??? ? power good output the power good output is an open-drain output and requires a pull up resistor. when the output voltage is 70% below its set voltage, pgood will be pulled low. it is held low until the output voltage returns to within the allowed tolerances once more. during soft-start, pgood is actively held low and only allowed to transition high after soft-start is over and the output voltage has reached 90% of its set voltage. under output voltage protection-hiccup mode for the ic, hiccup mode of under voltage protection (uvp) is provided. when the fb voltage drops below half of the feedback reference voltage, v fb , the uvp function will be triggered and the ic will shut down for a period of time and then recover automatically. the hiccup mode of uvp can reduce input current in short-circuit conditions. having a lower ripple current reduces not only the esr losses in the output capacitors but also the output voltage ripple. highest efficiency operation is achieved by reducing ripple current at low frequency, but it requires a large inductor to attain this goal. for the ripple current selection, the value of i l = 0.24(i max ) will be a reasonable starting point. the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below a specified maximum, the inductor value should be chosen according to the following equation : vin pgood vcc boot fb sw 9 8 1 2, 3, 4, 5 6 l r1 r2 v out v in RT8287 11 c boot c out c in ss 10 r t c ss en pgood r3 c c 7 q1 r en 100k chip enable 100k gnd 12, 13, 15 (exposed pad) agnd 14 47nf vin pgood vcc boot fb sw 9 8 1 2, 3, 4, 5 6 l r1 r2 v out v in RT8287 11 c boot c out c in ss 10 r t c ss en pgood r3 c c 7 r en 100k 100k r en2 gnd 12, 13, 15 (exposed pad) agnd 14 47nf inductor selection for a given input and output voltage, the inductor value and operating frequency determine the ripple current. the ripple current i l increases with higher v in and decreases with higher inductance.
RT8287 11 ds8287-03 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. the inductor's current rating (caused a 40 c temperature rising from 25 c ambient) should be greater than the maximum load current and its saturation current should be greater than the short circuit peak current limit. please see table 2 for the inductor selection reference and it is highly recommended to keep inductor value as close as possible to the recommended inductor values for each v out as shown in table 1. component supplier series di mens ion s (m m) tdk vlf10045 10 x 9.7 x 4.5 tdk slf12565 12.5 x 12.5 x 6.5 taiyo yuden nr8040 8 x 8 x 4 table 2. suggested inductors for typical application circuit out in rms out(max) in out v v i = i 1 vv ? this formula has a maximum at v in = 2v out , where i rms = i out / 2. this simple worst case condition is commonly used for design because even significant deviations do not offer much relief. choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. for the input capacitor, one 22 f low esr ceramic capacitors are recommended. for the recommende d capacitor, please refer to table 3 for more detail. table 3. suggested capacitors for c in and c out the selection of c out is determined by the required esr to minimize voltage ripple. moreover, the amount of bulk capacitance is also a key for c out selection to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response. the output ripple, v out , is determined by : out l out 1 viesr 8fc ?? ?? + ?? ?? higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. thermal shutdown thermal shutdown is implemented to prevent the chip from operating at excessively high temperatures. when the junction temperature is higher than 150 c, the chip will shut down the switching operation. the chip will automatically resume switching, once the junction temperature cools down by approximately 30 c. input and output capacitors selection the input capacitance, c in , is needed to filter the trapezoidal current at the source of the high side mosfet. to prevent large ripple current, a low esr input capacitor sized for the maximum rms current should be used. the rms current is given by : location component supplier part no. capacitance ( f) case size c in murata grm32er71c226m 22 1210 c in tdk c3225x5r1c226m 22 1210 c out murata grm31cr60j476m 47 1206 c out tdk c3225x5r0j476m 47 1210 c out murata grm32er71c226m 22 1210 c out tdk c3225x5r1c226m 22 1210
RT8287 12 ds8287-03 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. emi consideration since parasitic inductance and capacitance effects in pcb circuitry would cause a spike voltage on sw pin when high side mosfet is turned-on/off, this spike voltage on sw may impact on emi performance in the system. in order to enhance emi performance, there are two methods to suppress the spike voltage. one way is by placing an r-c snubber (r s *, c s *) between sw and gnd and locating them as close as possible to the sw pin, as shown in figure 5. reference circuit with snubber and enable timing control thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for wdfn-14l 4x3 package, the thermal resistance, ja , is 60 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (60 c/w) = 1.667w for wdfn-14l 4x3 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curve in figure 6 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. figure 6. derating curve of maximum power dissipation vin pgood vcc boot fb sw 9 8 1 2, 3, 4, 5 6 l r1 r2 v out v in RT8287 11 c boot c out c in ss 10 r t c ss en pgood r3 c c 7 r en * 100k c en * c s * r s * * : optional gnd 12, 13, 15 (exposed pad) agnd 14 47nf figure 5. another method is by adding a resistor in series with the bootstrap capacitor, c boot , but this method will decrease the driving capability to the high side mosfet. it is strongly recommended to reserve the r-c snubber during pcb layout for emi improvement. moreover, reducing the sw trace area and keeping the main power in a small loop will be helpful on emi performance. for detailed pcb layout guide, please refer to the section layout considerations. 0.00 0.30 0.60 0.90 1.20 1.50 1.80 0 255075100125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb
RT8287 13 ds8287-03 june 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. layout considerations follow the pcb layout guidelines for optimal performance of the ic. ` keep the traces of the main current paths as short and wide as possible. ` put the input capacitor as close as possible to the device pins (vin and gnd). ` sw node is with high frequency voltage swing and should be kept at small area. keep analog components away from the sw node to prevent stray capacitive noise pickup. figure 7. pcb layout guide ` connect feedback network behind the output capacitors. keep the loop area small. place the feedback components near the ic. ` connect all analog grounds to a common node and then connect the common node to the power ground behind the output capacitors. ` an example of pcb layout guide is shown in figure 7 for reference. vin sw sw sw agnd gnd gnd ss vcc sw boot pgood en fb 13 12 11 1 2 3 4 5 14 69 10 gnd 15 78 c in c boot v out c out gnd v out c ss r t r1 r2 l gnd place the input and output capacitors as close to the ic as possible. sw should be connected to inductor by wide and short trace and keep sensitive components away from this trace. place the feedback as close to the ic as possible.
RT8287 14 ds8287-03 june 2012 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. outline dimension w-type 14l dfn 4x3 package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 3.900 4.100 0.154 0.161 d2 3.250 3.350 0.128 0.132 e 2.900 3.100 0.114 0.122 e2 1.650 1.750 0.065 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018

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